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LTC3775 1 3775fa typical application features applications description high frequency synchronous step-down voltage mode dc/dc controller the ltc ? 3775 is a high ef? ciency synchronous step-down switching dc/dc controller that drives an all n-channel power mosfet stage from a 4.5v to 38v input supply voltage. a patented line feedforward compensation circuit and a high bandwidth error ampli? er provide very fast line and load transient response. high step-down ratios are made possible by a low 30ns minimum on-time, allowing extremely low duty cycles. mosfet r ds(on) current sensing maximizes ef? ciency. alternatively, a sense resistor can be used for higher cur- rent limit accuracy. continuous monitoring of the voltages across the top and bottom mosfets allows cycle-by-cycle control of the inductor current, con? gurable by external resistors. the soft-start function controls the duty cycle during start-up, providing a smooth output voltage ramp up. the operating frequency is user programmable from 250khz to 1mhz and can be synchronized to an external clock. n wide v in range: 4.5v to 38v n line feedforward compensation n low minimum on-time: t on(min) < 30ns n powerful onboard mosfet drivers n leading edge modulation voltage mode control n 0.75%, 0.6v reference voltage accuracy over temperature n v out range: 0.6v to 0.8v in n programmable, cycle-by-cycle peak current limit n sense resistor or r ds(on) current sensing n programmable soft-start n synchronizable fixed frequency from 250khz to 1mhz n selectable pulse-skipping or forced continuous modes of operation n low shutdown current: 14a typical n thermally enhanced 16-lead msop and 3mm 3mm qfn packages n automotive systems n telecom and industrial power supplies n point of load applications l , lt, ltc, ltm, linear technology, the linear logo are registered trademarks, no r sense and ultrafast are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5408150, 5481178, 5705919, 6580258, 5847554, 5055767. 0.1f 0.36h 470f 2.5v 2 330f 35v v in 5v to 28v v out 1.2v 15a 3775 ta01a 4.7f 330pf 3.9nf 57.6k 39.2k 4.7k 10k 10k 3.16k 0.01f tg v in LTC3775 sgnd sense i limt i limb intv cc ss bg pgnd comp boost sw freq fb load current (a) 30 efficiency (%) power loss (w) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3775 ta01b 0 1 2 3 4 5 0 0.1 efficiency power loss v in = 12v v out = 1.2v continuous mode sw freq = 500khz ef? ciency and power loss vs load current
LTC3775 2 3775fa absolute maximum ratings supply voltage v in ......................................................... C0.3v to 40v boost ................................................... C0.3v to 46v boost-sw ............................................... C0.3v to 6v sw ............................................................ C5v to 40v i limt .............................................................C0.3v to v in sense .............................................................C5v to v in intv cc ......................................................... C0.3v to 6v (note 1) 16 15 14 13 5 6 7 8 top view ud package 16-lead (3mm s 3mm) plastic qfn 9 10 11 12 4 3 2 1 i limt i limb fb comp sw v in sense intv cc run/ shdn mode/sync boost tg ss freq sgnd bg 17 pgnd t jmax = 125c, ja = 68c/w, jc = 4.2c/w (note 3) exposed pad (pin 17) is pgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 mode/sync run/ shdn i limt i limb fb comp ss freq 16 15 14 13 12 11 10 9 boost tg sw v in sense intv cc bg sgnd top view 17 pgnd mse package 16-lead plastic msop t jmax = 125c, ja = 40c/w (note 3) exposed pad (pin 17) is pgnd, must be soldered to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range LTC3775eud#pbf LTC3775eud#trpbf ldjk 16-lead (3mm 3mm) plastic qfn C40c to 85c LTC3775iud#pbf LTC3775iud#trpbf ldjk 16-lead (3mm 3mm) plastic qfn C40c to 125c LTC3775emse#pbf LTC3775emse#trpbf 3775 16-lead plastic msop C40c to 85c LTC3775imse#pbf LTC3775imse#trpbf 3775 16-lead plastic msop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ run/ shdn ................................................... C0.3v to 6v fb, mode/sync ................................... C0.3v to intv cc freq, i limb , ss ..................................... C0.3v to intv cc intv cc rms currents... .........................................50ma operating junction temperature range (note 2) .................................................. C40c to 125c storage temperature range ................... C65c to 150c
LTC3775 3 3775fa electrical characteristics symbol parameter conditions min typ max units input supply v in v in supply voltage l 4.5 38 v i vin input dc supply current v fb = 0.7v (note 5) v run = 0v 3.5 14 ma a run/ shdn pin v run run/ shdn pin enable threshold 1.19 1.22 1.25 v v shdn run/ shdn pin shutdown threshold v run/ shdn rising 0.74 v v shdn (hyst) run/ shdn pin shutdown threshold hysteresis 140 mv i run run/ shdn pin source current v run/ shdn = 0v v run/ shdn = 1.5v C1 C5 a a error ampli? er v fb feedback pin voltage l 0.597 0.5955 0.600 0.603 0.6045 v v v fb feedback voltage line regulation 4.5v < v in < 38v 0.01 %/v v out output voltage load regulation 1v < v comp < 2v (note 6) 0.01 0.1 % i fb fb pin input current v fb = 0.6v C50 50 na i comp comp pin output current sourcing, v comp = 0v sinking, v comp = 2v C0.5 1 C1 60 ma ma f 0db error ampli? er unity-gain crossover frequency (note 6) 25 mhz soft-start i ss ss pin source current v ss = 0v C1 a r ss ss pin pull-down resistance in current limit 1.3 k current limit i limb i limb source current v ilimb = 1v l C9 C10 C11 a i limt i limt sink current v ilimt = 12v l 90 100 110 a i sense sense pin input current 1a v ilimt(max) topside current limit threshold (v in -sense) v ilimt = 0.1v l 90 100 110 mv v ilimb(max) bottom side current limit threshold (pgnd-sw) v ilimb = 0.5v l 80 100 120 mv intv cc low dropout voltage regulator intv cc ldo regulator output voltage 4.9 5.2 5.5 v v intvcc(line) intv cc line regulation 7.5v < v in < 38v 0.01 %/v v intvcc(load) intv cc load regulation i intvcc = 0ma to 20ma C1 C0.1 % v dropout intv cc regulator dropout voltage (v in C v intvcc )i intvcc = 20ma 0.35 v v uvlo intv cc uvlo voltage intv cc rising hysteresis 3.0 3.6 0.5 4.2 v v the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c (note 2). v in = 12v, v run = 5v, unless otherwise speci? ed.
LTC3775 4 3775fa electrical characteristics the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c (note 2). v in = 12v, v run = 5v, unless otherwise speci? ed. symbol parameter conditions min typ max units oscillator f osc oscillator frequency r set = 39.2k l 425 500 575 khz f high maximum oscillator frequency l 1000 khz f low minimum oscillator frequency l 250 khz f sync external sync frequency range with reference to free running C20 20 % t on(min) tg minimum on-time (notes 6, 8) v mode/sync = 0v 30 ns t off(min) tg minimum off-time (note 6) 300 ns dc max maximum tg duty cycle f osc = 500khz l 90 % v mode mode/sync threshold mode/sync rising 1.2 v v mode(hyst) mode/sync hysteresis 430 mv r mode/sync mode/sync input resistance to sgnd 50 k driver bg r up bottom gate (bg) pull-up on-resistance 2.5 tg r up top gate (tg) pull-up on-resistance 2.5 bg r down bottom gate (bg) pull-down on-resistance 1.0 tg r down top gate (tg) pull-down on-resistance 1.5 bg, tg t 2d bottom gate off to top gate on delay top switch-on delay time c l = 3300pf (note 7) 15 ns tg, bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c l = 3300pf (note 7) 15 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3775 is tested under pulsed load conditions such that t j t a . the LTC3775e is guaranteed to meet speci? cations from 0c to 85c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3775i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these speci? cations is determined by speci? c operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja (in c/w) is the package thermal impedance. note 3: failure to solder the exposed pad of the ud package to the pc board will result in a thermal resistance much higher than 68c/w. note 4: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise speci? ed. note 5: supply current in normal operation is dominated by the current needed to charge and discharge the external mosfet gates. this current will vary with supply voltage and the external mosfets used. note 6: guaranteed by design, not subject to test. note 7: rise and fall times are measured using 10% and 90% levels. delay and nonoverlap times are measured using 50% levels. note 8: the LTC3775 leading edge modulation architecture does not have a minimum tg pulse width requirement. the tg minimum pulse width is limited by the sw node rise and fall times.
LTC3775 5 3775fa typical performance characteristics ef? ciency vs load current ef? ciency vs input voltage load regulation line regulation fb voltage vs temperature load step in forced continuous mode positive load step in forced continuous mode negative load step in forced continuous mode load step in pulse-skipping mode load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3775 g01 0 0.1 v in = 12v v out = 1.2v sw freq = 500khz first page circuit pulse-skipping mode continuous mode input voltage (v) 4 40 efficiency (%) 50 60 70 80 100 8 12 16 20 3775 g02 24 28 90 15a load 1a load v out = 1.2v continuous mode sw freq = 500khz first page circuit load current (a) 0 1.194 v out (v) 1.196 1.198 1.200 1.202 48 12 16 3775 g03 1.204 1.206 26 10 14 v in = 12v sw freq = 500khz first page circuit input voltage (v) 4 1.194 v out (v) 1.196 1.198 1.200 1.202 1.206 8 12 16 20 3775 g02 24 28 1.204 v out = 1.2v load = 1a first page circuit temperature (c) C50 fb voltage (mv) 601 602 603 25 75 3775 g05 600 599 C25 0 50 100 125 598 597 v out(ac) 100mv/div i l 10a/div i load 10a/div 50s/div 3775 g06 v in = 12v v out = 1.2v load step = 0a to 10a to 0a mode/sync = 0v sw freq = 500khz first page circuit v out(ac) 100mv/div v sw 20v/div i l 10a/div i load 10a/div 5s/div 3775 g07 v in = 12v v out = 1.2v load step = 0a to 10a mode/sync = 0v sw freq = 500khz first page circuit v out(ac) 100mv/div v sw 20v/div i l 10a/div i load 10a/div 5s/div 3775 g08 v in = 12v v out = 1.2v load step = 10a to 0a mode/sync = 0v sw freq = 500khz first page circuit v out(ac) 100mv/div i l 10a/div i load 10a/div 50s/div 3775 g09 v in = 12v v out = 1.2v load step = 1a to 11a to 1a mode/sync = intv cc sw freq = 500khz first page circuit
LTC3775 6 3775fa typical performance characteristics pulse-skipping mode waveform with 0.1a load switching frequency vs temperature duty cycle vs v comp i limt vs temperature i limt vs input voltage i limb vs temperature i run vs temperature shutdown current vs input voltage temperature (c) C50 450 switching frequency (khz) 460 480 490 500 550 520 0 50 75 3775 g11 470 530 540 510 C25 25 100 125 v comp (v) 0.6 0 duty cycle (%) 10 30 40 50 100 70 1.0 1.4 1.6 3775 g12 20 80 90 60 0.8 1.2 1.8 2.0 v in = 5v v in = 12v v in = 24v v in = 40v temperature (c) C50 90 i limt (a) 92 96 98 100 110 104 0 50 75 3775 g13 94 106 108 102 C25 25 100 125 input voltage (v) 4 90 i limt (a) 92 96 98 100 110 104 12 20 24 3775 g14 94 106 108 102 816 28 32 40 36 temperature (c) C50 9.0 i limb (a) 9.2 9.6 9.8 10.0 11.0 10.4 0 50 75 3775 g15 9.4 10.6 10.8 10.2 C25 25 100 125 temperature (c) C50 C2.0 i run (a) C1.8 C1.4 C1.2 C1.0 0 C0.6 0 50 75 3775 g16 C1.6 C0.4 C0.2 C0.8 C25 25 100 125 input voltage (v) 4 0 input current (a) 5 10 15 12 16 20 24 28 32 36 35 3775 g17 840 20 25 30 v out(ac) 100mv/div i l 2a/div v sw 10v/div 5s/div 3775 g10 v in = 12v v out = 1.2v load = 0.1a mode/sync = intv cc sw freq = 500khz first page circuit output short-circuit waveform i l 20a/div v ss 1v/div 20s/div 3775 g25 v in = 12v v out = 1.2v c ss = 0.01f first page circuit 0a load
LTC3775 7 3775fa shutdown current vs temperature temperature (c) C50 0 shutdown current (a) 2 6 8 10 20 14 0 50 75 3775 g18 4 16 18 12 C25 25 100 125 typical performance characteristics quiescent current vs intv cc intv cc load regulation intv cc dropout intv cc dropout vs temperature bg turn-on waveform driving renesas rjk0301 bg turn-off waveform driving renesas rjk0301 intv cc (v) 3.6 quiescent current (ma) 3 4 5 4.8 5.6 3775 g19 2 1 0 4.0 4.4 5.2 6 7 8 6.0 intv cc load current (ma) 0 $ intv cc (%) C0.4 C0.2 0 40 3775 g20 C0.6 C0.8 C0.5 C0.3 C0.1 C0.7 C0.9 C1.0 10 20 30 50 v in = 12v intv cc load current (ma) 0 intv cc dropout voltage (v) C0.4 C0.2 0 40 3775 g21 C0.6 C0.8 C1.0 10 20 30 50 t a = 25c temperature (c) C50 C25 C1.0 intv cc dropout voltage (v) C0.6 0 0 50 75 3775 g22 C0.8 C0.2 C0.4 25 100 125 load current = 20ma bg 1v/div 0v 20ns/div 3775 g23 v in = 12v v out = 1.2v load = 1a mosfet: renesas rjk0301 bg 1v/div 0v 20ns/div 3775 g24 v in = 12v v out = 1.2v load = 1a mosfet: renesas rjk0301
LTC3775 8 3775fa pin functions i limt (pin 1/pin 3): topside current limit set point. this pin has an internal 100a pull-down current, allowing the topside current limit threshold to be programmed by an external resistor connected to v in . see current limit applications. i limb (pin 2/pin 4): bottom side current limit set point. this pin has an internal 10a pull-up current, allowing the bottom side current limit threshold to be programmed by an external resistor connected to sgnd. see current limit applications. fb (pin 3/pin 5): error ampli? er input. the fb pin is connected to a resistive divider from v out to sgnd. the feedback loop compensation network is also connected to this pin. comp (pin 4/pin 6): error ampli? er output. use an rc network between the comp pin and the fb pin to compen- sate the feedback loop for optimum transient response. ss (pin 5/pin 7): soft-start. connect this pin to an external capacitor, c ss , to implement a soft-start function. when the voltage on the ss pin is less than the 0.6v internal reference, the LTC3775 regulates the v fb voltage to the ss pin voltage instead of the 0.6v reference. freq (pin 6/pin 8): frequency set. a resistor connected from this pin to sgnd sets the free-running frequency of the internal oscillator. see applications information section for resistor value selection details. sgnd (pin 7/pin 9): signal ground. all the internal low power circuitry returns to the sgnd pin. all feedback and soft-start connections should return to sgnd. sgnd should be kelvin connected to a single point near the negative terminal of the v out bypass capacitor. bg (pin 8/pin 10): bottom gate drive. this pin drives the gate of the bottom n-channel synchronous switch mosfet. this pin swings from pgnd to intv cc . intv cc (pin 9/pin 11): internal 5.2v regulator output. the gate driver and control circuits are powered from this voltage. bypass this pin to power ground with a low esr ce- ramic capacitor of value 4.7f or greater (x5r or better). sense (pin 10/pin 12): topside current sensing input. connect this pin to the switch node of the converter for top mosfet r ds(on) current sensing. alternatively, this pin can be connected to a sense resistor at the drain of the top mosfet for more accurate current limit. v in (pin 11/pin 13): main input supply. bypass this pin to pgnd with a low esr ceramic capacitor of value 1f or greater (x5r or better). sw (pin 12/pin 14): switch node. connect this pin to the source of the upper power mosfet. this pin is also used as the input to the bottom side current limit comparator and the zero-crossing reverse current comparator. tg (pin 13/pin 15): top gate drive. this pin drives the gate of the top n-channel mosfet. the tg driver draws power from the boost pin and returns to the sw pin, providing true ? oating drive to the top mosfet. boost (pin 14/pin 16): top gate driver supply. this pin should be decoupled to sw with a 0.1f low esr ceramic capacitor. an external schottky diode from intv cc to boost creates a ? oating charge-pump supply at boost. no other external supplies are required. mode/sync (pin 15/pin 1): pulse-skipping mode enable/ sync pin. this multifunction pin provides pulse-skipping mode enable/disable control and an external clock input for synchronization of the internal oscillator. pulling this pin below 1.2v (dc) or driving it with an external logic-level syn- chronization signal disables pulse-skipping mode operation and forces continuous operation. pulling the pin above 1.2v enables pulse-skipping mode operation. this pin has an internal 50k pull-down resistor connected to sgnd. run/ shdn (pin 16/pin 2): enable/shutdown input. pull- ing this pin above 1.22v enables the controller. forcing this pin below 1.22v causes the driver outputs to pull low. pulling this pin below 0.74v forces the LTC3775 into shutdown mode. while in shutdown, the intv cc regulator and most internal circuitry turns off and the supply current drops below 14a. this pin has an internal 1a pull-up current that allows the LTC3775 to power up if this pin is left ? oating. pgnd (exposed pad pin 17/exposed pad pin 17): power ground. the bg driver returns to this pin. connect pgnd to the source of the bottom power mosfet and the v in and intv cc bypass capacitors. pgnd is electrically iso- lated from sgnd. the exposed pad of the qfn and msop packages is connected to pgnd. (qfn/msop)
LTC3775 9 3775fa block diagram + C pgnd tg boost i limb v ilimb v in r ilimb r sense sense intv cc 10a intv cc d b l c b c out v out 3775 bd q t sw irev mode 0.6v ea pwm + C pgnd 0.2 ? v ilimb cblim + C ctlim + switch logic and antishoot- through bg q b pgnd fb fb c2 comp sgnd + C + C + C max + C 1a intv cc i ss mode 3.6v uvlo en 0.6v v in v in intv cc intv cc ext sync line feedforward mode/sync detect overtemp ref 5.2v reg osc ss 0.66v v in + + C c vcc c ss c1 c3 r3 r2 50k r a r b ss mode/sync freq r set r5 r4 run/ shdn shdn v in i run 1a chip shutdown 1.22v intv cc + C 0.74v r ilimt i limt intv cc 100a
LTC3775 10 3775fa applications information operation (refer to block diagram) the LTC3775 is a constant frequency, voltage mode con- troller for dc/dc step-down converters. it is designed to be used in a synchronous switching architecture with two external n-channel mosfets. for circuit operation, please refer to the block diagram. the LTC3775 uses voltage mode control in which the duty cycle is controlled directly by the error ampli? er output. the error ampli? er adjusts the voltage at the comp pin by comparing the v fb pin with the 0.6v internal refer- ence. when the load current increases, it causes a drop in the feedback voltage relative to the reference. the comp voltage then rises, increasing the duty cycle until the LTC3775 output feedback voltage again matches the reference voltage. in normal operation, the top mosfet is turned on when the pwm comparator changes state and is turned off by the internal oscillator. the pwm comparator maintains the proper duty cycle by comparing the error ampli? er output (after being compensated by the line feedfor- ward multiplier) to a sawtooth waveform generated by the oscillator. when the top mosfet is turned off, the bottom mosfet is turned on until the next cycle begins, or if pulse-skipping mode operation is enabled, until the inductor current reverses as determined by the reverse current comparator. feedback control the LTC3775 senses the output voltage at v out with an internal feedback op amp (see block diagram). this is a true op amp with a low impedance output, 80db of open- loop gain and a 25mhz gain-bandwidth product. the positive input is connected to an internal 0.6v reference, while the negative input is connected to the fb pin. the output is connected to comp , which is in turn connected to the line feedforward circuit and from there to the pwm generator. at steady state, as shown in the block diagram, the output of the switching regulator is given the following equation v out = v ref ?1 + r a r b unlike many regulators that use a transconductance (g m ) ampli? er, the LTC3775 is designed to use an inverting summing ampli? er topology with the fb pin con? gured as a virtual ground. this allows the feedback gain to be tightly controlled by external components. in addition, the voltage feedback ampli? er allows ? exibility in choosing pole and zero locations. in particular, it allows the use of type 3 compensation, which provides a phase boost at the lc pole frequency and signi? cantly improves the control loop phase margin. in a typical LTC3775 circuit, the feedback loop consists of the line feedforward circuit, the modulator, the external inductor, the output capacitor and the feedback ampli? er with its compensation network. all these components affect loop behavior and need to be accounted for in the loop compensation. the modulator consists of the pwm generator, the output mosfet drivers and the external mosfets themselves. the modulator gain varies linearily with the input voltage. the line feedforward circuit com- pensates for this change in gain, and provides a constant gain from the error ampli? er output to the inductor input regardless of input voltage. from a feedback loop point of view, the combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from comp to the inductor input and has a gain roughly equal to 30v/v. it has fairly benign ac behavior at typical loop compensation frequencies with signi? cant phase shift appearing at half the switching frequency. the external inductor/output capacitor combination makes a more signi? cant contribution to loop behavior. these components cause a second order lc roll-off at the output with 180 phase shift. this roll-off is what ? lters the pwm waveform, resulting in the desired dc output voltage, but this phase shift causes stability issues in the feedback loop and must be frequency compensated. at higher frequencies, the reactance of the output capacitor approaches its esr, and the roll-off due to the capacitor stops, leaving C20db/decade and 90 of phase shift.
LTC3775 11 3775fa applications information figure 1 shows a type 3 ampli? er. the transfer function of this ampli? er is given by the following equation: v comp v ou t = C1 + sr2c1 () 1 + s(r a + r3)c3 sr a c1 + c2 () 1 + s(c1|| c2 )r2 () 1 + sc3r3 ( ) the rc network across the error ampli? er and the feed- forward components r3 and c3 introduce two pole-zero pairs to obtain a phase boost at the system unity-gain frequency, f c . in theory, the zeros and poles are placed symmetrically around f c , and the spread between the zeros and the poles is adjusted to give the desired phase boost at f c . however, in practice, if the crossover frequency is much higher than the lc double-pole frequency, this method of frequency compensation normally generates a phase dip within the unity bandwidth and creates some concern regarding conditional stability. if conditional stability is a concern, move the error ampli- ? ers zero to a lower frequency to avoid excessive phase dip. the following equations can be used to compute the feedback compensation component values: f switching frequency f lc f r sw lc out esr = = = 1 2 1 2 e esr out c choose: f crossover frequency f ff c sw zerr lc == == 10 1 2 1( ) r rc f f rrc ff zres c a perr esr 21 5 1 233 2 1 () () == + () = = = == 1 2212 5 1 233 2 rc c ff rc pres c (||) () required error ampli? er gain at frequency f c : a v(crossover) 40log 1 + f c f l c 2 C20log 1 + f c f e sr 2 C20log a mod () 20log r2 r a ? 1 + f lc f c 1 + f p2(res) f c + f p2(res) Cf z2(res) f z2(re s) 1 + f c f e sr + f lc f esr Cf l c 1 + f p2(res) f c where a mod is the modulator and line feedforward gain and is equal to: a vdc v v v vv mod in max max saw = () ? ?. . / 40 0 95 125 30 once the value of resistor r a and the pole and zero loca- tions have been decided, the values of c1, r2, c2, r3 and c3 can be obtained from the above equations. compensating a switching power supply feedback loop is a complex task. the applications shown in this data sheet show typical values, optimized for the power components shown. though similar power components should suf? ce, substantially changing even one major power component may degrade performance signi? cantly. stability also may depend on circuit board layout. to verify the calculated component values, all new circuit designs should be prototyped and tested for stability. C + v out v ref r a r3 c3 r2 c1 gain (db) c2 fb r b comp freq C1 C1 +1 gain phase boost 0 phase (deg) C90 C180 C270 C380 3775 f01 figure 1. type 3 ampli? er compensation
LTC3775 12 3775fa applications information output overvoltage protection an overvoltage comparator, max, guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. run/shutdown the LTC3775 can be put into a low power shutdown mode with quiescent current <14a by pulling the run/ shdn pin below 0.74v. the run/ shdn pin can also be used as an accurate external uvlo (undervoltage lockout) input with a threshold of 1.22v. the driver outputs stay low if this pin is <1.22v. the external resistive divider r4 and r5 shown in the block diagram can be used to set the uvlo level based on v in . the v in voltage at which the switching starts is given by the following formula: uvlo (upper) = 1.22v ? (1 + r4/r5) C (1a ? r4) the run/ shdn pin has an internal 1a pull-up for default turn-on if this pin is left ? oating. this 1a pull-up current is included in the above uvlo calculation. when run/ shdn goes above 1.22v, this pull-up current is increased to 5a. this provides some amount of hysteresis to the uvlo threshold. the lower uvlo level becomes: uvlo (lower) = 1.22v ? (1 + r4/r5) C (5a ? r4) so the amount of hysteresis is given by: uvlo (hysteresis) = 4a ? r4 soft-start the LTC3775 includes a soft-start circuit that provides a smooth output voltage ramp during start-up. the ss pin requires an external capacitor, c ss , to gnd with the value determined by the required soft-start time. an internal 1a current source charges c ss . when the voltage on the ss pin is less than the 0.6v internal reference, the LTC3775 regulates the v fb voltage to the ss pin voltage instead of the 0.6v reference. as the ss voltage rises linearly from 0v to 0.6v and beyond, the output voltage, v out , rises smoothly from zero to its ? nal value. the total soft-start time can be calculated as: t c a softstart ss = 09 1 .? the ss pin is pulled low in the following conditions: during an ldo undervoltage condition (intv cc < 3.6v), during shutdown (run pin < 1.22v), during an overtemperature condition (t j > 165c) and during current limit. if either the top or bottom current limit comparator trips, the ss pin is pulled low until the inductor current regu- lates at around the current limit setting. once the fault is cleared, ss will start charging up allowing the duty cycle and output voltage to increase gradually. due to the cur- rent limit action on the ss pin, it is important to avoid an overcurrent condition during start-up of the power supply, or v out will fail to start up properly. 0.74v + C + C 1.22v turn off tg en 4a run r4 r5 3775 f02 i run 1a v in shdn LTC3775 chip shutdown figure 2. run pin control figure 3. typical start-up waveform for a buck converter using the LTC3775 i l 5a/div v out 0.5v/div v ss 1v/div 2ms/div 3775 f03 v in = 12v v out = 1.2v c ss = 0.01f mode = 0v sw freq = 500khz switchover from pulse- skipping to continuous mode
LTC3775 13 3775fa applications information to prevent discharging a pre-biased v out , the LTC3775 always starts switching in pulse-skipping mode up to ss = 0.54v, regardless of the mode selected by the mode/sync pin. thus if v out > 0v during power-up, v out will remain at the pre-biased voltage (if there is no load) until the ss voltage catches up with v out , after which v out will track the ss ramp. the LTC3775 reverts to the selected mode once ss > 0.54v. constant switching frequency the internal oscillator can be programmed from 250khz to 1mhz with an external resistor from the freq pin to ground, in order to optimize component size, ef? ciency and noise for the speci? c application. the internal oscillator can also be synchronized to an external clock connected to the mode/sync pin and can lock to a range of 20% of the programmed free-running frequency. when locked to an external clock, pulse-skipping mode operation is automatically disabled. constant frequency operation of- fers a number of bene? ts: inductor and capacitor values can be chosen for a precise operating frequency and the feedback loop can be similarly tightly speci? ed. noise generated by the circuit will always be at known frequen- cies. subharmonic oscillation and slope compensation, common headaches with constant frequency current mode switchers, are absent in voltage mode designs like the LTC3775. thermal shutdown the LTC3775 has a thermal detector that pulls the driver outputs low if the junction temperature of the chip ex- ceeds 165c. the thermal shutdown circuit has 25c of hysteresis. current limit the LTC3775 includes an onboard cycle-by-cycle current limit circuit that limits the maximum output current to a user-programmed level. the current limit circuit consists of two comparators, ctlim and cblim that monitor the voltage drop across the top and bottom mosfets respec- tively. since the mosfet s effective resistance, r ds(on) , is low during its on-time, the voltage drop from the drain to source is proportional to the current ? ow. alternatively, for better accuracy, the topside current may be monitored with a sense resistor. the bene? t of having two comparators is to allow continu- ous monitoring and cycle-by-cycle control of the inductor current regardless of the operating duty cycle. in high duty cycle operation the top mosfet, q t , is on most of the time. thus, a high side comparator is necessary to limit the output current during high duty cycle operation. architectures that contain only one comparator to monitor the low side mosfet will not effectively limit the output current during high duty cycle operation. conversely, during low duty cycle operation, a low side comparator is neces- sary to limit the output current. another common current sensing scheme uses a sense resistor in series with the inductor to allow continuous monitoring. however, this scheme restricts the range of v out due to the common mode range of the current limit comparator. the LTC3775 does not have this v out restriction. figure 4 shows the current limit circuitry. the top current limit comparator, ctlim monitors the current through the top mosfet, q t , when tg is high. if the inductor current exceeds the current limit threshold when q t is on, q t turns off immediately and the bottom mosfet, q b , turns on. the sense pin is the input for ctlim. for applications where figure 4. LTC3775 current limit circuit + + C 100a r ilimb (opt) 10a 0.2 ? v ilimb r ilimt v in LTC3775 r sense sense ctlim turn off tg + C cblim extend bg i limb sw i limt tg q t v in bg q b v out 3775 f04 pgnd sgnd
LTC3775 14 3775fa applications information the upper mosfet s r ds(on) is used to sense current, connect the sense pin to the source of q t (the sw node). alternatively, for accurate current sensing, connect this pin to a sense resistor located at the drain of q t . the reference input of ctlim is connected to the i limt pin. connect an external resistor, r ilimt , from the i limt pin to v in to set the the current limit threshold. the voltage at the sense pin drops as the inductor current increases. ctlim trips if the voltage at the sense pin goes below the voltage at the i limt pin causing tg to pull low and turn off q t . the bottom current limit comparator, cblim, monitors the current through the bottom mosfet, q b , when bg is high. if the inductor current exceeds the current limit threshold when q b is on, q b remains on until the current drops below the threshold. the sw pin is the input for cblim. the reference input to cblim is derived from the voltage at the i limb pin. connect an external resistor, r ilimb , from the i limb pin to sgnd to set the current limit threshold. the inductor current ? ows from pgnd to sw when q b is on (for a positive load current). the sw node is therefore a negative voltage. the LTC3775 inverts the voltage at the sw pin before comparing it with the attenuated voltage (5 ) at the i limb pin. bg stays high once cblim trips and tg remains low until the inductor current drops below the threshold. figure 5 shows typical waveforms during output overload. current limit blanking time the LTC3775 current limit circuit features a short blanking time following low-to-high and high-to-low transitions at the sw node. this prevents false tripping of the current limit circuit if there is ringing on the sw node. when the top gate, tg, goes high, the topside comparator, ctlim, waits for 200ns before turning on to monitor the sense voltage. likewise, when the bottom gate, bg, goes high the bottom side comparator, cblim, waits for 200ns before turning on to monitor the sw voltage. this means that the minimum tg and bg pulse is slightly more than 200ns during current limit. these blanking times do not, however, limit the duty cycle capability of the control loop. the LTC3775 control loop is capable of operation with a tg on-time as low as 30ns. if a sense resistor is employed on the top side, the LTC3775 automatically lowers the ctlim blanking time from 200ns to 100ns. the cblim blanking time remains at 200ns. the blanking time can be reduced when a sense resistor is used because the sense pin connects to the drain of the top mosfet which rings less than the sw node. the LTC3775 detects that a sense resistor is employed by checking that the sense pin stays high (equal to v in ) when bg is high. if the sense pin is connected to the sw node, sense will be at 0v when bg is high. the current sensing input pins the sense and i limt pins are inputs to the top current limit comparator, ctlim. the top current limit threshold is set by the resistor, r ilimt , connected to the i limt pin and the i limt pin 100a pull-down current. r ilimt should be placed close to the LTC3775 and the other end of r ilimt should run parallel with the sense trace to the kelvin sense connection underneath the sense resistor, as shown in figure 6. the sense resistor should be connected to the drain of the top power mosfet and the v in node using short, wide pcb traces. ideally, the top terminal of the sense resistors will be immediately adjacent to the posi- tive terminal of the input capacitor, as shown in figure 7a. this path is a part of the high di/dt loop formed by the sense resistor, top power mosfet, inductor and output capacitor. figure 5. typical waveforms during output overload v ss 1v/div i l 20a/div 20s/div 3775 f05 v in = 12v v out = 1.2v c ss = 0.01f first page circuit 0a load
LTC3775 15 3775fa figure 8. ef? ciency in pulse-skipping/forced continuous modes since the current limit comparator contains leading edge blanking, an external rc ? lter is not required for proper operation. however, an external ? lter can be designed by adding a capacitor across the sense and i limt pins (c f in figure 7a). the ? lter component should be placed close to the sense and i limt pins. if r ds(on) sensing is employed, the kelvin sense con- nection should run from the sense pin and the r ilimt resistor to the source and drain terminals of the top power mosfet respectively, as shown in figure 7b. the external rc ? lter should not be added since the source terminal is switching. the bottom side current limit threshold is set by the resis- tor, r ilimb , from the i limb pin to sgnd and the i limb pin 10a pull-up current. the voltage at ilimb is attenuated 5 internally before it is applied to the input of bottom current limit comparator, cblim. this voltage must be quiet. connect r ilimb from the i limb pin to a quiet ground near the LTC3775 sgnd pin. the other input of cblim is connected to the sw pin. the sw pin is also shared with the bottom gate driver and should be connected near the drain of the bottom mosfet, q b . pulse-skipping mode the LTC3775 can operate in one of two modes selectable with the mode/sync pin: pulse-skipping mode or forced continuous mode. pulse-skipping mode is selected when increased ef? ciency at light loads is desired, as shown in figure 8. in this mode, the bottom mosfet is turned off when inductor current reverses in order to minimize the ef? ciency loss due to reverse current ? ow. as the load current decreases (see figure 9), the duty cycle is reduced to maintain regulation until the minimum on-time (50ns) is reached. when the load decreases below this point, the LTC3775 begins to skip cycles to maintain regulation. this reduces the frequency and improves ef? ciency by minimizing gate charge losses. in forced continuous mode, the bottom mosfet is always on when the top mosfet is off, allowing the inductor cur- rent to reverse at low currents. this mode is less ef? cient due to switching, but has the advantages of better transient applications information r sense 3775 f06 to r limit to sense pin v in top mosfet drain v in c in c f r limit r sense 3775 f07a v in LTC3775 i limit sense tg sw figure 6. kelvin sense connection for topside current limiting sensing figure 7a. external filter for topside current sensing v in c in r limit q t 3775 f07b v in LTC3775 i limit sense tg sw figure 7b. kelvin connection for topside r ds(on) sensing load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3775 f08 0 0.1 v in = 12v v out = 1.2v sw freq = 500khz front page circuit pulse-skipping mode continuous mode
LTC3775 16 3775fa response at low load currents, constant frequency opera- tion, and the ability to maintain regulation when sinking current. see figure 8 for a comparison of the ef? ciency at light loads for each mode. in pulse-skipping mode, the LTC3775 reverse-current comparator, irev , monitors the sw pin for zero crossing when the bottom gate, bg, is high. it turns off bg if the inductor current reverses and the sw voltage goes above gnd. to prevent false tripping due to ringing on the sw node when bg is ? rst turned on, there is a blanking time of 200ns similar to the bottom side current limit blanking. under certain light load conditions, if the tg on-time is short, the inductor current may reverse during the irev blanking time but the LTC3775 will only turn off bg after the blanking time. in applications where a low value inductor is used, the high di/dt of the inductor ripple current together with the parasitic series inductance of the bottom mosfet, q b , and pcb trace inductance creates an opposing voltage to the voltage drop across the r ds(on) of qb. this can cause irev to trip early, before the inductor current reverses. the parasitic series inductance of the pcb trace can be minimized by connecting the sw pin closer to the drain of q b . intv cc regulator the LTC3775 features a p-channel low dropout linear regulator (ldo) that supplies power to the intv cc pin from the v in supply. intv cc powers the gate drivers and much of the LTC3775s internal circuitry. the ldo regulates the voltage at the intv cc pin to 5.2v when v in is greater than 6.5v. the intv cc pin must be bypassed to ground with a low esr (x5r or better) ceramic capacitor of at least 4.7f. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers. an internal undervoltage lockout (uvlo) monitors the volt- age on intv cc to ensure that the LTC3775 has suf? cient gate drive voltage. if the intv cc voltage falls below the uvlo threshold of 3.1v, the gate drive outputs remain low. thermal considerations the LTC3775 is offered in a 3mm 3mm qfn package (ud16) that has a thermal resistance r th(ja) of 68c/w and the msop (mse16) package has a thermal resistance of 40c/w. both packages have a lead pitch of 0.5mm. the regulator can supply up to 50ma of gate drive load cur- rent. the expected ldo load current can be calculated from the gate charge requirement of the external mosfet: i intvcc = (f sw ) ? (q g(qt) + q g(qb) ) + 3.5ma where: 3.5ma is the quiescent current of LTC3775 q g(qt) is the total gate charge of the top mosfet q g(qb) is the total gate charge of the bottom mosfet f sw is the switching frequency applications information figure 9. comparison of inductor current waveforms for pulse-skipping mode and forced continuous mode pulse-skipping mode forced continuous decreasing load current 0a 0a 0a 0a 0a 0a 3775 f09
LTC3775 17 3775fa the value of q g should come from the plot of v gs vs q g in the typical performance characteristics section of the mosfet data sheet. the value listed in the electrical speci? cations may be measured at a higher v gs , such as 10v, whereas the value of interest is at the 5v intv cc gate drive voltage. care must be taken to ensure that the maximum junction temperature of the LTC3775 is never exceeded. the junc- tion temperature can be estimated using the following equations: p diss = v in ? i intvcc t j = t a + p diss ? r th(ja) as an example of the required thermal analysis, consider a buck converter with a 24v input voltage and an output voltage of 3.3v at 15a. the switching frequency is 500khz and the maximum ambient temperature is 70c. the power mosfet used for this application is the vishay siliconix si7884dp , which has a typical r ds(on) of 7.5m at v gs = 4.5v and 5.5m at v gs = 10v. from the plot of v gs vs q g , the total gate charge at v gs = 5v is 18.5nc (the tem- perature coef? cient of the gate charge is low). one power mosfet is used for the top side and one for the bottom side. for the ud package: i intvcc = 3.5ma + 2 ? 18.5nc ? 500khz = 22ma p diss = 24v ? 22ma = 528mw t j = 70c + 528mw ? 68c/w = 105.9c in this example, the junction temperature rise is 35.9c. these equations demonstrate how the gate charge cur- rent typically dominates the quiescent current of the ic, and how the choice of the operating frequency and board heat sinking can have a signi? cant effect on the thermal performance of the solution. to prevent the maximum junction temperature from be- ing exceeded, the input supply current of the ic should be checked when operating in continuous mode (heavy load) at maximum v in . a trade-off between the operat- ing frequency and the size of the power mosfets may need to be made in order to maintain a reliable junction temperature. finally, it is important to verify the calculations by perform- ing a thermal analysis of the ? nal pcb using an infrared camera or thermal probe. operation at low supply voltage the LTC3775 has a minimum input voltage of 4.5v. the gate driver for the LTC3775 consists of a pmos pull-up and an nmos pull-down device, allowing the full intv cc voltage to be applied to the gates during power mosfet switching. nonetheless, care should be taken to deter- mine the minimum gate drive supply voltage (intv cc ) in order to choose the optimum power mosfets. important parameters that can affect the minimum gate drive volt- age are the minimum input voltage (v in(min) ), the ldo dropout voltage, the q g of the power mosfets, and the operating frequency. if the input voltage v in is low enough for the intv cc ldo to be in dropout, then the minimum gate drive supply voltage is: v intvcc = v in(min) C v dropout the ldo dropout voltage is a function of the total gate drive current and the quiescent current of the ic (typically 3.5ma). a curve of dropout voltage versus output cur- rent for the ldo is shown in figure 10. the temperature coef? cient of the ldo dropout voltage is approximately 6000ppm/c. see the intv cc regulator and thermal considerations sections for information about calculating the total quiescent current. applications information figure 10. intv cc ldo dropout voltage vs current intv cc load current (ma) 0 intv cc dropout voltage (v) C0.4 C0.2 0 40 3775 f10 C0.6 C0.8 C1.0 10 20 30 50 t a = 25c
LTC3775 18 3775fa after the calculations have been completed, it is impor- tant to measure the gate drive waveforms and the gate driver supply voltage (intv cc to pgnd) over all operating conditions (low v in , nominal v in and high v in , as well as from light load to full load) to ensure adequate power mosfet enhancement. consult the power mosfet data sheet to determine the actual r ds(on) for the measured v gs , and verify your thermal calculations by measuring the component temperatures using an infrared camera or thermal probe. operation at high supply voltage at high input voltages, the LTC3775s internal ldo can dissipate a signi? cant amount of power, which could cause the maximum junction temperature to be exceeded. conditions such as a high operating frequency, or the use of more than one power mosfet in parallel, could push the junction temperature rise to high levels. to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode at maximum v in . see the thermal considerations section for calculation of the maximum junction temperature. low duty cycle operation the LTC3775 uses a leading edge modulation architec- ture. because the top mosfet turns on when the pwm comparator trips, the top mosfet minimum on-time is not dependent on the propagation delay of the pwm comparator; it is only limited by the internal delays of the gate drivers and the rise/fall time of the power mosfet gate. this allows the LTC3775 to operate in very low duty cycle applications with a large step-down ratio. figure 11 shows minimum on-time waveforms for forced continuous mode operation. if pulse-skipping mode is selected, the LTC3775 allows the controller to skip pulses at light load, thereby reducing switching losses and improving the ef? ciency. figure 12 shows waveforms of the minimum on-time in pulse-skip- ping mode. if the tg on-time is less than the blanking time of the topside current limit comparator, ctlim, the topside comparator never trips during normal operation. the blanking time is 200ns for r ds(on) sensing and 100ns when a sense resistor is used. for tg on-times smaller than the topside blanking times, the LTC3775 relies on the bottom current limit comparator, cblim, to monitor the inductor current. if cblim trips, the LTC3775 starts to skip pulses and at the same time pulls down the soft-start capacitor to limit the duty cycle. if v out drops suf? ciently, the tg on-time can increase enough to turn on ctlim and limit the peak inductor current. the minimum on-time of the application circuit can be calculated at maximum v in : t v fv on min out sw in max () () ? = applications information figure 11. minimum on-time waveforms in forced continuous mode figure 12. minimum on-time waveforms in pulse-skipping mode v sw 10v/div tg 10v/div 20ns/div 3775 f11 v in = 28v v out = 0.6v load = 1a mode/sync = 0v sw freq = 1mhz v sw 10v/div tg 10v/div 20ns/div 3775 f12 v in = 28v v out = 0.6v load = 1a mode/sync = intv cc sw freq = 1mhz
LTC3775 19 3775fa high duty cycle operation the maximum duty cycle is limited by the LTC3775 internal oscillator reset time, the propagation delay of the pwm comparator and the boost pin supply refresh rate. the minimum off-time is typically 300ns. the top mosfet driver is biased from the ? oating bootstrap capacitor, c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage, v in , decreases to a voltage close to v out , the controller will enter dropout and attempt to turn on the top mosfet continuously. to avoid depleting the charge on the bootstrap capacitor, c b , the LTC3775 has an internal counter that turns on the bottom mosfet every eight cycles for 200ns to refresh the bootstrap capacitor. figure 13 shows maximum duty cycle operation with the 200ns boost pin supply refresh. step-down v in to v out ratios, another consideration is the minimum on-time of the LTC3775 (see the minimum on-time considerations section). a ? nal consideration for operating frequency is that in noise-sensitive communica- tions systems, it is often desirable to keep the switching noise out of a sensitive frequency band. the LTC3775 uses a constant frequency architecture that can be programmed over a 250khz to 1mhz range with a single resistor from the freq pin to ground, as shown in figure 14. the nominal voltage on the freq pin is 1.22v, and the current that ? ows from this pin is used to charge and discharge an internal oscillator capacitor. the value of r set for a given operating frequency can be chosen from figure 14 or from the following equation: r set (k ) = 19500 f(khz ) the oscillator can also be synchronized to an external clock applied to the mode/sync pin with a frequency in the range of 20% of the programmed free-running frequency set by the freq pin. in this synchronized mode, pulse- skipping mode operation is disabled. the clock high level must exceed 1.5v for a minimum of approximately 25ns to engage the feature. the bottom mosfet will turn-on following the rising edge of the external clock. applications information figure 13. maximum duty cycle waveforms r set value (k) 0 frequency (khz) 1000 900 800 700 600 500 400 300 200 80 3775 f14 20 40 60 100 70 10 30 50 90 figure 14. frequency set resistor (r set ) value bg 5v/div tg 5v/div 2s/div 3775 f13 v in = 4.5v v out = 4.2v load = 0a sw freq = 500khz oscillator reset boost pin supply refresh external components selection operating frequency the choice of operating frequency and inductor value is a trade-off between ef? ciency and component size. low frequency operation improves ef? ciency by reducing mosfet switching losses and gate charge losses. however, lower frequency operation requires more inductance for a given amount of ripple current, resulting in a larger induc- tor size and higher cost. if the ripple current is allowed to increase, larger output capacitors may be required to maintain the same output ripple. for converters with high top mosfet driver supply an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from
LTC3775 20 3775fa intv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + intv cc . the boost capacitor needs to store at least 100 times the gate charge required by the top mosfet. in most applications a 0.1f to 1f x5r or x7r dielectric capacitor is adequate. the reverse breakdown of the schottky diode, d b , must be greater than v in(max) . power mosfet selection the LTC3775 requires two external n-channel power mosfets, one for the top (main) switch and one for the bottom (synchronous) switch. important parameters for the power mosfets are the threshold voltage v (gs)th , breakdown voltage v (br)dss , maximum current i ds(max) , on-resistance r ds(on) and input capacitance. the gate drive voltage is set by the 5.2v intv cc supply. consequently, logic-level threshold mosfets must be used in LTC3775 applications. if the intv cc voltage is expected to drop below 5v, then sub-logic level threshold mosfets should be considered. pay close attention to the v (br)dss speci? cation because most logic-level mosfets are limited to 30v or less. the mosfets selected should have a v (br)dss rating greater than the maximum input voltage and some margin should be added for transients and spikes. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (figure 15). the curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate- to-drain capacitance. the ? at portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain voltage drops. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is ? at) is speci? ed for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve speci? ed v ds values. to estimate the capacitance c miller , take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage speci? ed. c miller is the most important selec- tion criteria for determining the transition loss term in the top mosfet but is not directly speci? ed on mosfet data sheets. c rss and c os are speci? ed sometimes but de? nitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: top gate duty cycle = v out v i n bottom gate duty cycle = v in Cv out v i n the power dissipation for the top and bottom mosfets at maximum output current are given by: p top = v out v in i out max) 2 () (t (top) () r ds(on)(max) () + v in 2 i out(max) 2 r dr () c miller () ? 1 intv cc Cv th(il) + 1 v th(il) ?f sw p bot = v in Cv out v in i out( ax) 2 () mt(top) () r ds(on)(max) () where: r dr = effective top driver resistance v th(il) = mosfet data sheet speci? ed typical gate threshold voltage at the speci? ed drain current applications information + C v ds v in v gs miller effect q in ab c miller = (q b C q a )/v ds v gs v + C 3775 f15 figure 15. gate charge characteristics
LTC3775 21 3775fa c miller = calculated miller capacitance using the gate charge curve from the mosfet data sheet f sw = switching frequency both mosfets have conduction losses (i 2 r) while the topside n-channel equation includes an additional term for transition losses, which peak at the highest input volt- age. for v in < 12v, the high current ef? ciency generally improves with larger mosfets, while for v in > 12v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher ef? ciency. the bottom mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the bottom switch is on close to 100% of the period. schottky diode selection an optional schottky diode connected between the sw node (cathode) and the source of the bottom mosfet (anode) conducts during the dead time between the conduction of the power mosfet switches. it is intended to prevent the body diode of the bottom mosfet from turning on and storing a charge during the dead time, which can cause a modest (about 1%) ef? ciency loss. the diode can be rated for about one half to one ? fth of the full load current since it is on for only a fraction of the duty cycle. in order for the diode to be effective, the inductance between it and the bottom mosfet must be as small as possible, mandating that these components be placed next to each other on the same layer of the pc board. input capacitor selection the input bypass capacitor has three primary requirements: its esr must be low to minimize the supply drop when the top mosfets turn on, its rms current capability must be adequate to withstand the ripple current at the input, and its capacitance must be large enough to maintain the input voltage until the input supply can respond. generally, a capacitor (particularly a non-ceramic type) that meets the ? rst two parameters will have far more capacitance than is required to keep capacitance-based droop under control. the input capacitors voltage rating should be at least 1.4 times the maximum input voltage. in continuous mode, the source current of the top n-channel mosfet is approximately a square wave of duty cycle v out / v in . the maximum rms capacitor current is given by: ii vvv v rms out max out in out in () () C this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. medium voltage (20v to 35v) ceramic, tantalum, os-con and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramics have high voltage coef? cients of capacitance and may have audible piezoelectric effects; tantalums need to be surge-rated; os-cons suffer from higher inductance, larger case size and limited surface mount applicability; and electrolytics higher esr and dryout may require several to be used in parallel. sanyo os-con svp , svpd series; sanyo poscap tqc series or aluminum electrolytic capacitors from panasonic wa series or cornel dublilier spv series, in parallel with a couple of high performance ceramic capacitors, can be used as an effective means of achieving low esr and high bulk capacitance. output capacitor selection the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple v out is approximately bounded by: v out i l esr + 1 8?f sw ?c ou t where i l is the inductor ripple current. applications information
LTC3775 22 3775fa i l may be calculated using the equation: i l = v out l?f sw 1C v out v i n since i l increases with input voltage, the output ripple voltage is highest at maximum input voltage. typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering and has the necessary rms current rating. manufacturers such as sanyo, panasonic and cornell dublilier should be considered for high performance through-hole capacitors. the os-con semiconductor electrolyte capacitor available from sanyo has a good (esr)(size) product. an additional ceramic capacitor in parallel with os-con capacitors is recommended to offset the effect of lead inductance. in surface mount applications, multiple capacitors may have to be connected in parallel to meet the esr or tran- sient current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are both available in surface mount con? gurations. new special polymer surface mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent output capacitor choices are the sanyo poscap tpd, poscap tpb, avx tps, avx tpsv, the kemet t510 series of surface mount tantalums, kemet ao-caps or the panasonic sp series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. other capacitor types include nichicon pl series and sprague 595d series. consult the manufacturer for other speci? c recommendations. inductor selection the inductor in a typical LTC3775 application circuit is chosen based on the required ripple current, its size and its saturation current rating. the inductor should not be al- lowed to saturate below the hard current limit threshold. the inductor value sets the ripple current, which is com- monly chosen at around 40% of the anticipated full load current. lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and out- put voltage ripple. highest ef? ciency is obtained at low frequency with small ripple current. however, achieving high ef? ciency requires a large inductor and generates higher output voltage excursion during load transients. there is a trade-off between component size, ef? ciency and operating frequency. given a speci? ed limit for ripple current, the inductor value can be obtained using the fol- lowing equation: l = v out f sw ? i l(max ) ?1C v out v in(max ) once the value for l is known, the type of inductor must be selected. high ef? ciency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m ? cores. a variety of inductors designed for high current, low voltage applications are available from manu- facturers such as sumida, panasonic, coiltronics, coilcraft and toko. see the current limit programming section for calculation of the inductor saturation current. current limit programming if current sensing is implemented with a sense resistor, the topside current limit can be programmed by setting r ilimt as follows: r ilimt = cf ? r sense ? i o(max) + 0.5 ? i l i limit(min ) where: r sense = sense resistor value i o(max) = maximum output current i l = inductor ripple current (refer to the output capaci- tor selection section). i limt(min) = i limt pin minimum pull-down current of 90a cf = correction factor to provide safety margin and account for r sense tolerance; use a value of cf = 1.2 is reasonable. applications information
LTC3775 23 3775fa if topside mosfet r ds(on) sensing is used, the r ilimt value is calculated from the following equation: r ilimit = t ?r ds(on)(qt)(max) ? i o(max) + 0.5 ? i l i limit(min ) r ds(on)(qt)(max) is the maximum mosfet on-resistance typically speci? ed at 25c. the t term is a normalization factor (unity at 25c) accounting for the signi? cant variation in on-resistance with temperature, typically about 0.5%/c as shown in figure 16. for a maximum junction temperature of 100c, using a value t = 1.4 is reasonable. the bottom side current limit can be programmed by setting r ilimb as follows: r ilimb = 5? t ?r ds(on)(qb)(max) ? i o(max) + 0.5 ? i l i limb(min ) where i limb(min) = i limb pin minimum pull-up current of 9a. the resulting values of r ilimt and r ilimb should be checked in an actual circuit to ensure that the current limit kicks in as expected. circuits that use mosfets with low value r ds(on) for current sensing should be checked carefully. the pcb trace resistance and parasitic inductance can signi? cantly change the actual current limit threshold. care should be taken to shorten the pcb trace at the sense, sw and pgnd connections. the current limit setting also determines the worst-case peak current ? owing in the inductor during an overload condition. the inductor saturation current rating needs to be higher than the worst-case peak inductor current: i ir r l sat limt max ilimt sense min () () () ? or i ir r l sat limt max ilimt dson qt min () () ()( ) ? or i ir r l sat limb max ilimb dson qb min () () ()( ) .? ? () 02 i limt(max) = i limt pin maximum pull-down current of 110a i limb(max) = i limb pin maximum pull-up current of 11a r ds(on)(qt)(min) and r ds(on)(qb)(min) are the power mosfet minimum on-resistances. mosfet data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. a reasonable assumption is that the minimum r ds(on) is the same percentage below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. the saturation current rating for the inductor should be determined at the maximum input voltage, maximum output current and the maximum expected core temperature. the saturation current ratings for most commercially available inductors drop at high temperature. to verify safe operation, it is a good idea to characterize the inductors core/winding temperature under the following conditions: 1) worst-case operating conditions, 2) maximum allowable ambient temperature and 3) with the power supply mounted in the ? nal enclosure. thermal characterization can be done by placing a thermocouple in intimate contact with the winding/core structure, or by burying the thermocouple within the windings themselves. applications information junction temperature (c) C50 r t normalized on-resistance 1.0 1.5 150 0.5 0 0 50 100 2.0 3775 f16 figure 16. typical mosfet r ds(on) vs temperature
LTC3775 24 3775fa mode/sync pin the mode/sync pin is a dual function pin that can be used to program the operating mode or to synchronize the switching frequency to an external clock. pulse- skipping mode is enabled when the mode/sync pin is above 1.2v. the mode is forced continuous when the pin is below 1.2v. if this pin is left ? oating, an internal 50k pull-down resistor defaults the selection to forced continuous mode. during power-up, the LTC3775 overrides this mode selection and operates in pulse-skipping mode to prevent the discharge of a pre-biased output capacitor. the internal LTC3775 oscillator can be synchronized to an external clock with a signal greater than 1.5v . a low-to-high transition on the mode/sync pin resets the oscillator sawtooth waveform (high) and forces tg low (see figure 17).the external oscillator frequency must be within 20% of the frequency programmed by the r set resistor, or else the part will revert to free-running mode. the internal oscillator locks to the external clock after the second clock transition is received. when external synchronization is detected, the LTC3775 will operate in forced continuous mode. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3775. check the following in your layout: 1. keep the signal and power grounds separate. the signal ground consists of the LTC3775 sgnd pin and the (C) terminal of v out . the power ground consists of the optional schottky diode anode, the source of the bottom side mosfet, and the (C) terminal of the input capacitor. connect the signal ground to the (C) terminal of the output capacitor. also, try to connect the (C) terminal of the output capacitor as close as possible to the (C) terminals of the input capacitor. 2. the high di/dt loop formed by the top n-channel mosfet, the bottom mosfet and the c in capacitor should have short leads and pc trace lengths to minimize high frequency noise and voltage stress from inductive ringing. 3. connect the drain of the topside mosfet directly to the (+) plate of c in , and connect the source of the bottom side mosfet directly to the (C) terminal of c in . this capacitor provides the ac current to the mosfets. 4. place the ceramic c intvcc decoupling capacitor im- mediately next to the ic, between intv cc and sgnd. likewise, the c b capacitor should also be next to the ic between boost and sw. 5. place the small-signal components away from high frequency switching nodes (boost, sw, tg and bg). 6. for optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (kelvin connection), staying away from any high dv/dt traces. place the divider resistors near the LTC3775 in order to keep the high impedance fb node short. 7. for applications with multiple switching power convert- ers connected to the same input supply, make sure that the input ? lter capacitor for the LTC3775 is not shared with other converters. ac input current from another converter could cause substantial input voltage applications information external clock at mode/sync pin pwm ramp tg 3775 f17 figure 17. external synchronization
LTC3775 25 3775fa ripple, and this could interfere with the operation of the LTC3775. a few inches of pc trace or wire (l ? 100nh) between c in of the LTC3775 and the actual source v in should be suf? cient to prevent input noise interference problems. 8. the top current limit programming resistor, r ilimt , should be placed close to the LTC3775 and the other end of r ilimt should run parallel to the sense trace to the kelvin sense connection underneath the sense resistor. 9. the bottom current limit programming resistor, r ilimb , should be placed close to the LTC3775 and the other end of r ilimb should connect to sgnd. 10. the sw pin should be connected to the drain of the bottom mosfet. checking transient response for all new LTC3775 pcb circuits, transient tests need to be performed to verify the proper feedback loop operation. the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to i load ? (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time, v out can be monitored for excessive overshoot or ringing which would indicate a stability problem. measuring transient response presents a challenge in two respects: obtaining an accurate measurement and gen- erating a suitable transient for testing the circuit. output measurements should be taken with a scope probe directly across the output capacitor. proper high frequency prob- ing techniques should be used. do not use the 6" ground lead that comes with the probe! use an adapter that ? ts on the tip of the probe and has a short ground clip to ensure that inductance in the ground path doesnt cause a bigger spike than the transient signal being measured. the typical probe tip ground shield is spaced just right to applications information pulse generator 0v to 10v 100hz, 1% duty cycle LTC3775 locate close to the output v out 10k 50 7 irfz44 or equivalent r load 3775 f18 figure 18. transient load generator span the leads of a typical output capacitor. in general, it is best to take this measurement with the 20mhz bandwidth limit on the oscilloscope turned on to limit high frequency noise. note that microprocessor manufacturers typically specify ripple 20mhz, as energy above 20mhz is gener- ally radiated (and not conducted) and does not affect the load even if it appears at the output capacitor. now that we know how to measure the signal, we need to have something to measure. the ideal situation is to use the actual load for the test, switching it on and off while watching the output. if this isnt convenient, a current step generator is needed. this generator needs to be able to turn on and off in nanoseconds to simulate a typical switching logic load, so stray inductance and long clip leads between the LTC3775 and the transient generator must be minimized. figure 18 shows an example of a simple transient generator. be sure to use a noninductive resistor as the load element. many power resistors use an inductive spiral pattern and are not suitable for use here. a simple solution is to take ten 1/4w ? lm resistors and wire them in parallel to get the desired value. this gives a noninductive resistive load which can dissipate 2.5w continuously or 250w if pulsed with a 1% duty cycle, enough for most LTC3775 circuits. solder the mosfet and the resistor(s) as close to the output of the LTC3775 circuit as possible and set up the signal generator to pulse at a 100hz rate with a 1% duty cycle. this pulses the LTC3775 with 100s transients 10ms apart, adequate for viewing the entire transient recovery time for both positi ve and negative transitions while keeping the load resistor cool.
LTC3775 26 3775fa applications information design example as a design example, take a supply with the following speci? cations: v in = 5v to 26v (12v nominal), v out = 1.2v 5%, i out(max) = 15a, f = 500khz. first, verify the minimum on-time which occurs at maxi- mum v in : t v vkhz ns on min () . . = ()( ) = 12 26 500 92 3 the minimum on-time is lower than the top current limit comparator blanking time of 100ns with sense resistor sensing. the controller will rely on the bottom mosfet r ds(on) sensing at high v in . next, verify the maximum duty cycle which occurs at minimum v in : m a ximum duty cycle v v . % == 12 5 24 this is below the LTC3775 maximum duty cycle of 90%. next, calculate r set to give the 500khz operating frequency: rk set == 19500 500 39 next, choose the inductor value for about 40% ripple current at maximum v in : l = 1.2v 500khz () 0.4 () 15a ( ) 1C 1.2 26 = 0.38h select 0.36h which is the nearest standard value. the resulting maximum ripple current is: i l = 1.2v 500khz () 0.36h ( ) 1C 1.2v 26 v = 6.4a next, choose the top and bottom mosfet switch. since the drain of each mosfet will see the full supply voltage 26v (max) plus any ringing, choose a 30v mosfet to provide a margin of safety. because the top mosfet is on for a short time, a renesas rjk0305dpb (r ds(on) = 13m (max), c miller = q gd /10v = 150pf, v gs(th) = 2.5v, ja = 40c/w) is suf? cient. check its power dissipation at current limit with = 100c = 1.4: p top = 1.2v 26 v 15a () 2 ? 1.4 ? 13m () + 26v () 2 15a 2 2.5 () 150pf () 1 5.2 C 2.5 + 1 2.5 500khz = 0.19w + 0.73w = 0.92w and double check the assumed t j in the mosfet: t j = 70c + (0.92w)(40c/w) = 107c the junction temperatures will be signi? cantly less at nominal current, but this analysis shows that careful at- tention to heat sinking will be necessary. a renesas rjk0301dpb (r ds(on) = 4m (max), ja = 40c/w) is chosen for the synchronous mosfet. p bot = 26v C 1.2v 26 v 15a () 2 ? 1.4 ? 4m () = 1.26w and double check the assumed t j in the mosfet: t j = 70c + (1.26w)(40c/w) = 120c next, the intv cc ldo current is calculated: i intvcc = (500khz)(8nc + 32nc) + 3.5ma = 23.5ma and double check the t j in the LTC3775: t j = 70c + (23.5ma)(26v)(68c/w) = 112c next, set the current limit resistors with a sense resistor of 3m. r ilimt = 1.2 ? 3m ? 15a + 0.5 ? 6.4a 90 a = 728 r ilimb = 5 ? 1.4 ? 4m ? 15a + 0.5 ? 6.4a 9 a = 56.62k use the next higher standard values of 732 and 57.6k.
LTC3775 27 3775fa applications information the worst-case peak inductor current based on a sense resistor tolerance of 1% is i l(sat) 110a ? 732 2.97m = 27.1a the input rms current is highest at v in(min) = 5v and i out(max) = 15a: ia vv v v a rms () = 15 12 5 12 5 64 .C. . c in is chosen for an rms current rating of >6.4a at 85c. for the output capacitor, two low esr os-con capacitors (470f/5m each) are used to minimize output voltage changes due to inductor current ripple and load steps. the ripple voltage will be: v out(ripple) = 6.4a ? 0.005 2 + 1 8 ? 500khz ? 470f ? 2 = 17.7mv however, a 0a to 15a load step will cause an output volt- age change of at least: v out(step) = (15a)(0.0025) = 37.5mv
LTC3775 28 3775fa typical applications 5v to 26v input, 1.2v/15a output at 500khz c b 0.1f c f 220pf l1 0.36h c out 470f 2.5v s 2 c in1 330f 35v v in 5v to 26v v out 1.2v 15a 3775 ta02 c vcc 4.7f c2 330pf c1 3.9nf r ilimb 57.6k r set 39.2k r2 4.7k r b 10k c out : sanyo 2r5tpd470m5 d b : cmdsh4e l1: ihlp-4040dz-er-r36-m11 q b : rjk0301dpb-00-j0 q t : rjk0305dpb-00-j0 r a 10k r sense 0.003 r ilimt 732 d b c ss 0.01f tg q t q b v in LTC3775 sgnd sense i limt i limb intv cc ss bg pgnd mode/sync run/ shdn comp boost sw freq fb + +
LTC3775 29 3775fa 8v to 36v input, 2.5v/10a output at 500khz l1 1.2h c out 330f 4v s 3 c in1 330f 35v v in 8v to 36v v out 2.5v 10a 3775 ta03 c vcc 4.7f c b 0.1f c2 330pf c3 1500pf c1 2200pf r ilimb 133k r set 39.2k r2 15k r b 3.16k c out : sanyo 4tpd330m d b : cmdsh4e l1: toko fda1254-1r2m q b ,q t : infineon bsz097n04ls r a 10k r3 390 d b r4 43.2k r ilimt 464 r sense 0.003 r5 10k c ss 0.01f i limt q t c f 220pf q b v in LTC3775 sgnd sense boost i limb intv cc ss bg pgnd mode/sync comp tg sw freq run/ shdn fb + + load step ef? ciency and power loss vs load current start-up i l 10a/div v out(ac) 100mv/div 50s/div 3775 ta03c v in = 12v v out = 2.5v load = 0a to 10a to 0a mode = 0v sw freq = 500khz load current (a) 0.01 40 efficiency (%) power loss (w) 50 60 70 80 0.1 1 10 3775 ta03b 30 20 10 0 90 100 4 3 2 1 0 5 v in = 12v v out = 2.5v continuous mode sw freq = 500khz efficiency power loss i l 5a/div v out 1v/div v ss 1v/div 2ms/div 3775 ta03d v in = 12v v out = 2.5v css = 0.01f mode = 0v sw freq = 500khz switchover from pulse- skipping to continuous mode typical applications
LTC3775 30 3775fa typical applications 24v input, 12v/5a output at 500khz c b 0.1f l1 4.7h c out 68f 16v s 2 c in1 330f 35v v in 24v v out 12v 5a 3775 ta04 c vcc 4.7f c2 330pf c1 3.3nf r ilimb 56.2k r set 39.2k r2 7.68k r b 10k c out : sanyo 16tqc68m d b : cmdsh4e l1: ihlp-4040dz-er-4r7-m11 q b , q t : rjk0305dpb-00-jo r a 191k r3 2.05k c3 330pf r ilimt 1.24k r4 69.8k r5 10k d b c ss 0.01f tg q t q b v in LTC3775 sgnd sense i limt i limb intv cc ss bg pgnd mode/sync comp boost sw freq run/ shdn fb + + load step ef? ciency and power loss vs load current start-up load current (a) 30 efficiency (%) power loss (w) 90 100 20 10 80 50 70 60 40 0.01 1 10 3775 ta04b 0 1.0 2.5 0.5 2.0 1.5 0 0.1 efficiency power loss v in = 24v v out = 12v continuous mode sw freq = 500khz i l 5a/div v out(ac) 200mv/div 50s/div 3775 ta04c v in = 24v v out = 12v load = 0a to 5a to 0a mode = 0v sw freq = 500khz i l 5a/div v out 5v/div v ss 1v/div 2ms/div 3775 ta04d v in = 24v v out = 12v css = 0.01f mode = 0v sw freq = 500khz switchover from pulse- skipping to continuous mode
LTC3775 31 3775fa package description ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691) 3.00 p 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 p 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 bottom viewexposed pad 1.45 p 0.10 (4-sides) 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 1 pin 1 notch r = 0.20 typ or 0.25 s 45 o chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 p 0.05 3.50 p 0.05 0.70 p 0.05 0.00 C 0.05 (ud16) qfn 0904 0.25 p 0.05 0.50 bsc package outline
LTC3775 32 3775fa package description msop (mse16) 0608 rev a 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 12345678 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 p 0.102 (.112 p .004) 2.845 p 0.102 (.112 p .004) 4.039 p 0.102 (.159 p .004) (note 3) 1.651 p 0.102 (.065 p .004) 1.651 p 0.102 (.065 p .004) 0.1016 p 0.0508 (.004 p .002) 3.00 p 0.102 (.118 p .004) (note 4) 0.280 p 0.076 (.011 p .003) ref 4.90 p 0.152 (.193 p .006) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop , exposed die pad (reference ltc dwg # 05-08-1667 rev a)
LTC3775 33 3775fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 8/10 msop package added. re? ected throughout the data sheet. 1 to 34
LTC3775 34 3775fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0810 rev a ? printed in usa related parts part number description comments ltc3854 small footprint wide v in range synchronous step-down dc/dc controller fixed 400khz operating frequency, 4.5v v in 38v, 0.8v v out 5.25v, 2mm 3mm qfn-12 ltc3851a/ ltc3851a-1 wide v in range synchronous step-down dc/dc controller p hase-lockable fixed operating frequency 250khz to 750khz, 4v v in 38v, 0.8v v out 5.25v, msop-16e, 3mm 3mm qfn-16, ssop-16 ltc3878/ ltc3879 no r sense ? constant on-time synchronous step-down dc/dc controller very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.8v v out 0.9v in , ssop-16, msop-16e, 3mm 3mm qfn-16 ltc3850/ ltc3850-1/ ltc3850-2 dual 2-phase, high ef? ciency synchronous step-down dc/dc controllers, r sense or dcr current sensing and tracking phase-lockable fixed operating frequency 250khz to 780khz, 4v v in 30v, 0.8v v out 5.25v ltc3860 dual, multiphase synchronous step-down dc/dc controller with diff amp and 3-state output drive operates with power blocks, drmos devices or external mosfets 3v v in 24v, t on(min) = 20ns ltc3853 triple output, multiphase synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed operating frequency 250khz to 750khz, 4v v in 24v, v out up to 13.5v typical application wide input range cpu power supply (refer to demo board dc1290a-b) tg v in v in LTC3775 pgnd sense i limt i limb intv cc intv cc cmdsh-4e r s1 (opt) bsc016no4lsg q2 d1 (opt) l1 wurth 744314110 1.1h q4 (opt) q3 (opt) 1 4 23 5 q1 infineon bsc093no4lsg v out intv cc run run mode ss c6 10nf r16 (opt) r9 56.2k bg mode/ sync comp boost sw freq fb 1 2 16 c3 330pf c2 0.022f c8 100pf c in5 0.1f 50v c1 0.1f r6 10k 1% r1 1.62k r15 0 r5 2k c4 4700pf r2 31.6k r s2 0 r sns2 (opt) r sns1 0.004 r3 4.7 r8 0 r7 1.82k 5 sgnd 7 15 4 6 3 11 14 10 17 9 12 8 13 r4 10k 1% c5 4.7f 10v 1 4 23 5 3775 ta05 c out4 100f 6.3v c out1 470f 4v sanyo poscap 4tpf470mu v out v out + v out 1.2v/10a gnd v out C c out2 470f 4v c out5 (opt) e3 j3 j4 e4 c out3 1f 6.3v x5r + + + c in2 4.7f 50v c in3 4.7f 50v v in + v in 5v to 36v gnd v in C c in4 (opt) e1 j1 j2 e2 c in1 100f 50v + v in = 5v to 36v v out = 1.2v/10a f s = 350khz intv cc 1 2 3 4 jp1 mode r13 1k mode pulse-skipping sync fcc sgnd sync e8 e6 v out v in 1 2 3 jp2 c7 (opt) r12 (opt) r14 (opt) on off run run e7 d2

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